The present invention relates generally to data processing systems, and more particularly to reliable data transfer in synchronous data processing systems.
As the operating speed of data processing systems such as microcomputers has increased in recent years, operating speeds of peripheral devices such as microprocessors and memory devices such as synchronous dynamic random access memory (SDRAM) have also increased to improve performance of such systems. There also has been an increase in the operating frequency of the busses connecting processors and peripherals. However, as the frequency increases, propagation delay and PVT variations play a more significant role in data transfer.
Typically, in synchronous data processing systems, there is a phase difference or skew between the clock and data signals transferred between the components such as a memory controller and a memory device. Such phase skew is incurred due to propagation delay and process, voltage and temperature (PVT) variations. As frequency increases, phase skew may increase, which can lead to incorrect data sampling during read or write operations.
One way of reducing the phase skew is by employing a phase lock loop (PLL) circuit for improving the data sampling. FIG. 1 is a block diagram of a conventional data processing system 10 having a PLL circuit 12. The data processing system 10 includes a memory controller 14 and a memory module 16. The memory controller 14 includes the PLL circuit 12 for compensating for any phase skew between clock and data signals transferred between the memory controller 14 and the memory module 16.
In operation, the memory controller 14 receives an input clock signal (IP_CLK) 18 from a clock signal generator (not shown) that is fed to read and write data buffers 20 and 22. The memory controller 14 also generates a memory clock signal 23 for the memory module 16. Here, data signals (IP_DATA and MEM_DATA) transmitted between the memory controller 14 and the memory module 16 are represented generally by reference numerals 24 and 26.
As illustrated, the memory clock signal (MEM_CLK) 23 is looped back half way between the memory controller 14 and the memory module 16 and a clock in signal (CLK_IN) 28 is fed to the PLL circuit 12 to generate a clock out signal (CLK_OUT) 30. This feedback mechanism improves data sampling. Thus, the clock signals observed by the memory controller 14 and the memory module 16 are aligned, thereby providing one complete cycle for data transfer during read and write operations. Although the PLL circuit 12 with the looped back signal CLK_IN 28 improves the data sampling of the system, it has a limitation in that it works only if the propagation delay between memory controller 14 and memory module 16 is less than one clock cycle.
FIG. 2 is a timing diagram of the data read and write cycles for the data processing system 10 of FIG. 1. In the illustrated embodiment, the memory clock signal and the looped back signal cycles are represented by reference numerals 50 and 52. The memory clock signals and the looped back signals 50 and 52 are phase aligned. Further, data signals launched by the memory controller 14 and received by the memory module 16 during a write operation are represented by reference numerals 54 and 56. Similarly, data signals transmitted by the memory module 16 and read by the memory controller 14 are represented by reference numerals 58 and 60 respectively.
In a write cycle, data (IP_DATA) 54 is launched from the write data buffer 22 at a positive edge of the clock signal 52 (IP_CLK which is phase aligned to CLK_IN) and is received by the memory module 16 as MEM_DATA 56. In a read cycle, MEM_DATA 58 is launched from the memory module 72 at a positive edge of the memory clock signal (MEM_CLK) 50 and is read by the memory controller 14 as IP_DATA 60.
As can be seen, the PLL circuit 12 fails to compensate for the phase skew during write and read cycles when the propagation delay is around one clock cycle or more, as indicated by reference numerals 62 and 64. Unfortunately, this may lead to incorrect data sampling.
In addition, the PLL circuits occupy significant area on the circuit board and are typically designed for a pre-determined frequency band, and characterization of such PLL circuits is tedious and, as mentioned above, susceptible to varying PVT conditions.
Therefore a need exists for a data processing system that allows for reliable data transfer given varying propagation delay and PVT conditions.